Hotwire Regulator Design Collaboration Project part 3

[JimmyM]

Solution to reduce sleep mode power drain.
Very early in our design discussion we lamented the parasitic loss created by the sampling divider. We came to the conclusion that is was small enough to forget about. But I wanted to solve that problem.
Some quick math:
For Vref: 1.1V
Vbat 40V
Sample divider: 360K & 10K
That leaves us with 0.108 mA drain

For Vref: 2.56V
Vbat 40V
Sample divider: 150K & 10K
That leaves us with 0.25 mA drain

That might seem quite small, but it's pretty large compared to the AVR sleep mode current of ~0.0006 mA.

So I had an epiphany. I've been working with some small FETs with a Gate Threshold of just 1.8V.

If a small N-FET is placed between the Upper resistor of the divider and the ADC input, it will isolate the ADC and disconnect the sampling divider current path. Since the AVR is driving the gate with 5V and the drain leg is, at most 1.1 or 2.56V above ground, that leaves us with 3.9-2.49V between the Drain and Gate. Well above the 1.8V Gate threshold. I tested this last night and it works great.

Sampling divider parasitic losses can be reduced to the leakage current of the FET. In the case of the one I used, <1 uA (0.0001 mA). The added component is an addition to complexity, but since these can be had in tiny SC-70 packages, the impact on space is very small.

 

[Alan B]

Solution to reduce sleep mode power drain.
Very early in our design discussion we lamented the parasitic loss created by the sampling divider. We came to the conclusion that is was small enough to forget about. But I wanted to solve that problem.
Some quick math:
For Vref: 1.1V
Vbat 40V
Sample divider: 360K & 10K
That leaves us with 0.108 mA drain

For Vref: 2.56V
Vbat 40V
Sample divider: 150K & 10K
That leaves us with 0.25 mA drain

That might seem quite small, but it's pretty large compared to the AVR sleep mode current of ~0.0006 mA.

So I had an epiphany. I've been working with some small FETs with a Gate Threshold of just 1.8V.

If a small N-FET is placed between the Upper resistor of the divider and the ADC input, it will isolate the ADC and disconnect the sampling divider current path. Since the AVR is driving the gate with 5V and the drain leg is, at most 1.1 or 2.56V above ground, that leaves us with 3.9-2.49V between the Drain and Gate. Well above the 1.8V Gate threshold. I tested this last night and it works great.

Sampling divider parasitic losses can be reduced to the leakage current of the FET. In the case of the one I used, <1 uA (0.0001 mA). The added component is an addition to complexity, but since these can be had in tiny SC-70 packages, the impact on space is very small.

Great idea, Jim. You may recall I had a somewhat different approach with an opto-isolator, which I chose not to implement at the present time. Your idea is simpler, but it unfortunately won't work on my particular design since I use the 5V range as well as the lower voltage ranges in my autoranging.

 

[JimmyM]

Great idea, Jim. You may recall I had a somewhat different approach with an opto-isolator, which I chose not to implement at the present time. Your idea is simpler, but it unfortunately won't work on my particular design since I use the 5V range as well as the lower voltage ranges in my autoranging.

Right. I had thought about your autoranging, but didn't realize you use the 5V (Vcc) Vref as well. Oh, well. Maybe future designs.

 

[Alan B]

The current drain is pretty low already, most battery setups will handle many months to a few years of standby. I often loosen the tailcap to reduce it further, but charging once every few months is not a bad idea anyway. Heck, standard NiMH cells have more self drain than the regulator! Also other regulators that are very popular have more drain than mine.

What would be perfect for this function is a small surface mount opto with an FET output.

 

[JimmyM]

The current drain is pretty low already, most battery setups will handle many months to a few years of standby. I often loosen the tailcap to reduce it further, but charging once every few months is not a bad idea anyway. Heck, standard NiMH cells have more self drain than the regulator! Also other regulators that are very popular have more drain than mine.

What would be perfect for this function is a small surface mount opto with an FET output.

I agree. It's pretty darned low to begin with. But it was always there in the back of my mind. The other night lying in bed it occurred to me.
An opto with an FET output would be perfect.
How about an opto isolated SSR.
Avago ASSR-301
In stock at Mouser:
ASSR-301

 

[Alan B]

I agree. It's pretty darned low to begin with. But it was always there in the back of my mind. The other night lying in bed it occurred to me.
An opto with an FET output would be perfect.
How about an opto isolated SSR.
Avago ASSR-301
In stock at Mouser:
ASSR-301

I suspect that most any opto-isolator would be fine, the current is so low.