Driver Board Layout Rules?

[Th232]

Background: I'm a 4th year mechatronics engineering student. I *think* I've got a handle on component selection, and my general layout skills are ok, but stuff like laying out components to minimise losses simply hasn't been covered. Sadly, power electronics is hardly covered in my degree.

Current knowledge: I've read the various datasheets and the recommendations in them, but I don't understand why some of those recommendations are made. Bypass caps &c. I understand, but the finer points of inductive and capacitive coupling are beyond me. For a more solid example, here's a driver I'm making based on the LT3590 from Linear Technology, what can I improve on?

Blue trace is Vin, hopefully the rest of it is fairly self-explanatory.

Also got a board with two drivers and an AVR controlling them, but I figure it's best to start with the more basic board first.

Any help would be greatly appreciated!

 

[TorchBoy]

How much current is it going to handle?

 

[Th232]

This one, not much, max is around 50 mA. One note in the datasheet says to minimise the length and area of the traces connected to SW, but then I suppose that would have to be balanced by how much power is lost by the increased resistance?

On the other hand, the more complex one I mentioned will output up to 1A, so hopefully the more I learn on this one the simpler the other one will be to fix.

 

[Th232]

Bump!

Anyone with any advice?:candle:

Can also provide the Eagle files if so needed.

 

[TorchBoy]

I suspect only a few CPFers are knowledgeable enough to give definite answers. If I was doing it I'd probably make some of those traces a bit thicker, but at only 50 mA for this particular driver there's no point.

 

[Th232]

Good point, driver design seems to be one of those things that isn't really discussed around here.

Well, looks like I'll try and find a suitably knowledgeable EE guy at uni.

 

[TorchBoy]

That's probably your best shot.

 

[DeadButAlive]

I've done a few buck/boost converter layouts and here are some things that I do to minimize unwanted harmonics...

1. Use planes (also called copper fills) for connectivity. If you're using a 4 (or more) layer board use one layer as a dedicated ground plane. This minimizes the "antenna effect" and reduces overall noise.
2. Group common references points together (i.e. - group SM resistors/caps with ground ends close to one another, power sides close, etc...) and then use the filled planes (mentioned above) to connect them. Especially on the ground side, common point connection minimizes feedback loops and resonances. (also larger planes can act as heatsinks for high-power components)
3. Keep as much physical separation as possible between filled plane edges - more separation = less capacitive coupling.
4. Remember that inductors are the noisiest things in the system, followed by anything that switches at high frequency (FETs, Schottky diodes, etc...). Try to use well shielded inductors and/or isolate them as much as possible - physically as well as electrically (again by using filled planes for connectivity instead of traces). KEEP THESE AS FAR FROM MICROS AND OTHER "SMART" ICs AS REASONABLY POSSIBLE.
5. Use decoupling caps (lots of them - not just on the supply but elsewhere in the circuit if necessary)
   

Its been forever since I used Eagle (I usually use Orcad) so I can't really be any help there, but I've done layout for quite a few switching power supplies and buck/boost converters. By following the above guidelines (as best I could - or at least as many as I could remember at the time) I've never had a problem. There's probably much more wisdom out there, but most of this I've gleaned from datasheets (I use a lot of Linear Technologies stuff, their datasheets are great), and plain old trial and error.

Gotta go for now, hope this helps - Good luck!

EDITED TO ADD: Also, if you're designing for low power it becomes important to isolate the high frequency switching components electrically (mainly from ground) to minimize capacitive coupling. In your schematic above these would be anything directly connected to the inductor and the trace/plane connected to the 'SW' lead of the IC. This "parasitic capacitance" can actually have quite a bit of cumulative effect at high voltage/high frequency and large surface areas (i.e. - filled plane connections) over long periods of time. But as you can see, this sort of stands in contrast to the first item in the list above - thus the trade-off game starts. Keep these traces short and/or planes small as possible to minimize both effects. --Mabye more to come if I can think of anything else to add--